The present invention concerns the transfer of data between ports in an input/output (I/O) device.
In an I/O device, such as a local area network adaptor card, data is transferred between a data port interfacing a host computer and a data port which receives and transmits I/O data.
Data flow within the I/O device is conventionally managed by a controller. For example, in a local area network adaptor card which interfaces an Ethernet Local Area Network to an Extended Industry Standard Architecture (EISA) bus, a DP8390 LAN Controller available from National Semiconductor, having a business address of 2900 Semiconductor Drive, Santa Clara Calif. 95052, may be used. The I/O device may be designed so that the controller manages data transfers in one of a number of ways.
For example, the controller may directly move data between a local area network (LAN) and a bus port. This solution, however, has several potential disadvantages. For example, most available controllers are not able to transfer data at a sufficiently high rate so the local area network and the bus are able to transfer data at maximum performance levels. This disadvantage is increased, for example when the controller transfers data in a word size which is smaller than the word size used by the bus. For instance, the DP8390 LAN controller transfers data in 16-bit words while the EISA bus performs 32-bit word transfers. Further using a controller to directly transfer data may incur significant software overhead in control software for the controller.
In order to increase bus performance, a first-in-first-out (FIFO) memory may be added to the bus interface. The controller may then queue data within the FIFO which is transferred on the bus. This allows for increased bus performance but increases data latency within the I/O device. Further, FIFO memories are expensive and consume a large area of the circuit board used in the implementation of the I/O device. Further, control circuits for FIFO memories can be complex. Also, there is still significant software overhead required for the controller to directly transfer data to the FIFO memories.
Alternately, the I/O device may use dual port memories and a memory map shared by the I/O device and the host computer system. However, dual port memories are extremely expensive and consume a large area of the circuit board used in the implementation of the I/O device. Further, shared memory maps are complex for configuring systems and require additional circuit overhead to decode addresses.